This invention relates to a synchronizing circuit for synchronizing an input pulse, which is asynchronously input from outside, with an internal clock signal.
A synchronizing circuit is generally used as an input circuit in a device (such as pulse transmission circuits, digital control circuits, and computers) in which signal processing progresses under the control of a clock pulse signal.
A typical example of this type of known synchronizing circuit is a device which employs R-S flip-flop. In this circuit, the R-S flip-flop (FF) is set by arrival of input pulses from exterior, and the logical "1" signal output from the set FF is supplied to a first input terminal of an AND gate. The second input of the AND gate is coupled to receive the clock pulse signal. When the "1" signal is supplied to the AND gate, the AND gate permits the clock pulse signal to be generated as an output signal of the synchronizing circuit. At this time, the R-S FF is reset by the output signal, and is returned to its original state.
In the synchronizing circuit thus arranged, the R-S FF is set by the randomly arrival input pulse, and is reset by the clock pulse generated at a predetermined timing. Jitter, for example, frequently gives rise to a problematic situation wherein the input pulse overlaps with or appears closer in time to the clock pulse. In this situation, the FF operation becomes instable. This may cause the synchronizing circuit to operate erroneously. For example, when the input pulse arrives during a period in which the clock pulse is raised, the set signal is pulled into--and cancelled by--the reset signal.
In the case where the set signal, i.e., the input pulse signal falls after the reset signal, i.e., the clock pulse signal falls, the R-S FF is set at the time the reset signal becomes "0", thus ensuring that the synchronizing circuit operates properly. When the pulse width of the input pulse is wide, the R-S FF is more stable. To prevent the cancellation of the set signal, the conventional synchronizing circuit is provided with an input pulse detecting circuit for changing the pulse width of the input pulse signal into a relatively long pulse width. The output signal from this detector, in place of the external input pulse, is input to the R-S FF.
When a pulse hoving an excessively wide pulse width is generated from the detector, the R-S FF is undesirably set a plural number of times due to the pulse, thereby providing unnecessary pulses. This occurs in the following case. The reset signal is generated during a period that set signal is input to the R-S FF, and the set signal inputting progresses after the reset signal has fallen. In other words, after the R-S FF is reset by the reset signal, it is set again by the set signal.
It is for this reason that the pulse width of the pulse signal from the detector must be set to the maximum value of those values preventing the generation of a plurality of output pulses by a single set signal.
The detector generally contains a delay circuit. The pulse width of the pulse from the detector can be adjusted by appropriately selecting the delay time of the delay circuit. The usual delay circuit is composed of a CR time constant circuit consisting of resistive and capacitive elements, for example, or cascade connected inverters consisting of transistors, for example. Those elements inevitably suffer from variations of their constants arising from the manufacturing stage or due to ambient temperature variation. Therefore, it is very difficult to obtain an exact delay time by the delay circuit. Therefore, in designing the delay circuit, the variation of the delay time must be considered. This makes it difficult to cause the detector to output the pulses with an desired and exact pulse width. This variation problem may be solved by using a compensating circuit for compensating for the delay time variation. This approach, however, requires a large pattern area of the semiconductor chip. This is problematic when it is assembled into the LSI chip.